JSSC 2024第6期Clocking & PLLsPLL

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL Pratap Tumkur Re

提出一种16GHz电荷泵锁相环，用于高效FMCW雷达信号生成。

16GHz, 29.3MHz/µs chirp slope, 41kHz rms-frequency error, 16.5mW

电荷泵锁相环FMCW雷达占空比两点调制时域校准

▸创新点1：引入占空比方案降低功耗（系统创新）。通过动态控制PLL的工作周期，显著降低平均功耗，适用于低功耗FMCW雷达系统，实测功耗仅为16.5mW。

▸创新点2：设计两点调制CP-PLL频率调制器（电路创新）。采用双路径调制结构实现快速启动和锁定，支持1.5GHz带宽的线性调频，锁定时间低于1µs。

▸创新点3：采用时域符号提取技术校准增益失配（方法创新）。通过时间域信号处理消除两点调制的增益失配，使频率误差降低至41kHz RMS。

▸创新点4：实现16GHz高频操作与高线性调频斜率（性能创新）。在16GHz载波下达成29.3MHz/µs的调频斜率，兼顾高频与快速调频需求。

Abstract

A 16-GHz charge-pump phase-locked loop (CP-PLL) for a robust duty-cycled frequency-modulated continuous-wave (FMCW) radar chirp generation is presented. A duty-cycling (DC) scheme is introduced to reduce the overall power consumption. To enable fast startup and fast locking, a two-point modulated CP-PLL frequency modulator is designed. To enable the two-point gain mismatch calibration a time-domain sign extraction technique is explored. The 16-GHz chirp generator achieves a 29.3-MHz/µs chirp slo