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A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control
提出一种27W无线功率收发器,采用紧凑单级调节Class-E架构,提升系统效率。
27W, 6.78MHz, 63.0% E2E效率, 80.0%峰值E2E效率
无线功率收发器Class-EGaN晶体管自适应死区控制高效率
▸创新点1:单级调节Class-E架构(系统创新)。将buck转换器与Class-E功率放大器合并为单一转换级,节省了一个电感和一个电容,显著提高了系统效率(峰值效率达83.7%),同时支持27W高功率输出。
▸创新点2:自适应占空比ZVS控制器(方法创新)。通过动态调节占空比实现零电压开关,无需外部阻抗调谐模块,解决了传统Class-E需固定50%占空比的限制,降低了系统复杂度和体积。
▸创新点3:HV-NMOS屏蔽推挽比较器(电路创新)。采用高压NMOS屏蔽技术直接检测高电压信号,无需电阻分压器,提升了电压检测精度(2.8ns快速上升沿)并避免信号失真。
▸创新点4:基于S/H反馈的自适应死区控制(方法创新)。通过采样保持环路动态优化死区时间,减少buck级反向导通和恢复损耗,进一步提升整体效率(E2E效率达80%)。
Abstract
This work presents a reconfigurable single-stage regulated Class-E (SSRE) wireless power transceiver that deliv- ers 27 W for wireless charging at 6.78 MHz. The power stage of the transmitter merges a buck and a Class-E power amplifier (PA) into one conversion stage, saving one inductor and one capacitor with improved system efficiency. Instead of using a bulky external impedance tuning block to ensure a 50% duty cycle operating point, the proposed Class-E zero-voltage switching (ZVS) controller allows the Class-E stage to work at an adaptive duty cycle without an off-chip tuning circuit. The high voltage and high current stress of the Class-E stage is handled by a GaN transistor, the driver of which uses an NMOS transistor for the high-side switch that realizes a rising edge of 2.8 ns with no overshoot. For directly sensing high voltage without using a resistor divider, an HV-NMOS shielded push-pull comparator is designed. An adaptive dead time control based on a sample-and- hold (S/H) feedback loop is proposed to reduce reverse conduction and recovery loss of the buck stage. The proposed solution demonstrates good trade-off among power level, efficiency, and power density. The SSRE WPT system delivers a maximum dc output power of 27 W with an end-to-end (E2E) efficiency of 63.0% if the receiver uses a traditional passive rectifier. The peak E2E efficiency of 80.0% is achieved at dc output power of 9.5 W; furthermore, in a two-chip differential transmitter configuration, the