A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations

Abstract

This article presents a low-cost PMOS-based 8T (P-8T) static random access memory (SRAM) compute-in- memory (CIM) macro that efficiently reduces the hardware cost associated with a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). By utilizing the bitline (BL) charge-sharing technique, the area and power consumption of the proposed DAC have been reduced while achieving similar conversion linearity compared to a conventional DAC. The BL charge-sharing also facilitates the multiply-accumulate (MAC) operation to produce variation-tolerant and linear outputs. To reduce ADC area and power consumption, a 4-bit coarse- fine flash ADC has been collaboratively used with an in-SRAM reference voltage generation, where the ADC reference voltages are generated in the same way as the MAC operation mechanism. Moreover, to find the suitable ADC sample range and resolution for our CIM macro, a CIM noise-considered accuracy simulation has been conducted. Based on the simulation results, a 4-bit ADC resolution with a cutoff ratio of 0.5 is chosen, maintaining high accuracy. The 256 × 80 P-8T SRAM CIM prototype chip has been fabricated in a 28-nm CMOS process. By leveraging charge- domain computing, the proposed CIM operates in a wide range of supply voltage from 0.6 to 1.2 V with an energy efficiency of 50.1-TOPS/W at 0.6 V . The accuracies of 91.26% and 65.20% are measured for CIFAR-10 and CIFAR-100 datasets, respectively. Compared to the state-of-the-art SRAM CIM wor