← 返回 JSSC 论文列表JSSC 2024第6期Data Converters28nmDACSRAM
A 28-nm 501-TOPSW P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharin
提出一种基于PMOS的8T SRAM存内计算宏设计，采用BL电荷共享技术降低DAC和ADC硬件成本。
28nm CMOS, 0.6-1.2V, 50.1-TOPS/W, CIFAR-10准确率91.26%
存内计算SRAM电荷共享ADC能效优化
▸BL电荷共享技术降低DAC面积和功耗
▸4位粗-细闪存ADC与SRAM内参考电压生成协同设计
▸电荷域计算实现宽电压范围工作（0.6-1.2V）
Abstract
This article presents a low-cost PMOS-based 8T
(P-8T) static random access memory (SRAM) compute-in-
memory (CIM) macro that efficiently reduces the hardware
cost associated with a digital-to-analog converter (DAC) and an
analog-to-digital converter (ADC). By utilizing the bitline (BL)
charge-sharing technique, the area and power consumption of
the proposed DAC have been reduced while achieving similar
conversion linearity compared to a conventional DAC. The BL
charge-sharing also facilitates th