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JSSC 2024第6期Power Management55nm

A 30-µW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout

一种低功耗、高动态范围的电流模式直接数字转换器,采用噪声整形三斜率量化器。
55nm CMOS, 30µW, 94.7dB SNDR, 136.5dB DR
电流模式直接数字转换器噪声整形低功耗高动态范围
创新点1:噪声整形三斜率量化器(方法创新)。通过引入三斜率量化器,实现了对热噪声和量化噪声的一阶噪声整形,显著提高了带外噪声抑制能力,有效提升了转换器的分辨率和动态范围。
创新点2:粗-细缩放式量化(方法创新)。采用粗-细缩放式量化技术,减少了转换时间,从而降低了动态偏置下电路模块的功耗,同时保持了高分辨率和高动态范围。
创新点3:斩波电流DAC(电路创新)。提出了一种斩波电流DAC技术,有效降低了电流DAC的1/f噪声,进一步提升了动态范围,适用于高精度电流传感应用。
创新点4:动态带宽调整(系统创新)。通过缩短转换时间,实现了采样频率和信号带宽的动态调整,支持从20 Hz到2 kHz的多种应用场景,适应不同电流传感需求。
Abstract
This article presents a low-power, high-resolution, high dynamic range (DR) current-mode direct-to-digital con- verter (CM-DDC) using a noise-shaping triple-slope quantizer. Both thermal and quantization noises can be first-order shaped out of band, increasing the resolution effectively. High resolution can be realized without using a high sampling rate or high-order shaping architecture. A coarse-fine zoom style quantization is exploited, which reduces the conversion time and, thus, the power consumption of active circuit blocks with dynamic biasing. On the circuit level, a chopped current digital-to-analog converter (DAC) is proposed to reduce 1/ f noise of the current DAC, enhancing the DR. The CM-DDC with light-emitting diode (LED) driver and digital control circuitry is implemented in a standard 55-nm CMOS process and characterized experimentally. The converter achieves a signal-to-noise and distortion-ratio (SNDR) of 94.7 dB and a cross-scale DR of 136.5 dB in 20-Hz bandwidth with 30-µW power for photoplethysmography (PPG)/near-infrared spectroscopy (NIRS) applications. Thanks to the shortened con- version time, the converter’s sampling frequency and signal bandwidth can be adjusted to 200 Hz and 2 kHz, achieving 90.5- and 79.2-dB SNDR, respectively, which allows various current sensing applications. The proposed CM-DDC is also validated with on-body chest PPG measurement.