A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers Chuangguo Wang

Abstract

Nanosecond-scale ON-chip delay is critical for inte- grated wideband self-interference cancellation (SIC) in full duplex (FD) system, especially for radio frequency (RF) domain SIC. In this article, we presented an FD receiver (RX) with multi- domain SICs using capacitor stacking (CS)-based delay cell in the RF canceller which breaks the trade-off among delay, loss, form-factor, and noise. In addition, a delay bandwidth (BW) expansion method is proposed to break the limitation of delay BW product, which is demonstrated in the BB canceller. A prototype is fabricated in 65 nm CMOS process. The proposed FD RX can operate in 0.5–4 GHz with a gain of 29–32 dB. At 2 GHz local oscillator (LO) frequency, the RF canceller can achieve a delay of ∼2–7.5 ns while consuming 10 mW. The baseband (BB) canceller can achieve a delay of 9–15 ns while consuming 4.4 mW. These large nanosecond-scale delays ensure 32–38 dB SIC over 20 MHz signal BW in case of applying a commercial circulator (isolation of 23–26 dB). In FD mode, the RF and BB cancellers degrade the RX noise figure (NF) by less than 0.9 and 0.4 dB at 2 GHz LO frequency, respectively. The RX power handling is improved by 11.5 dB. The active chip area is only 0.4 mm 2.