JSSC 2024第6期MemorySRAM

MACC-SRAM A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM M

提出一种基于电容耦合的多步累加存内计算SRAM宏，用于4位深度卷积神经网络推理。

128×128 9T1C单元阵列，6位SAR ADC

存内计算SRAM电容耦合卷积神经网络模数转换

▸采用多步累加电容耦合技术，节省66%的电容驱动能量

▸采用加法优先架构，节省60.7%面积和66.7%模数转换能耗

▸通过增加DNN模型稀疏性优化，减少39.4%电容驱动能量

Abstract

This article presents multistep accumulation capac- itor coupling static random-access memory (MACC-SRAM), capacitor-based in-memory computing (IMC) SRAM macro for 4-b deep convolutional neural network (DNN) inference. The macro can simultaneously activate all its 128 × 128 custom 9T1C bitcells to perform the vector–matrix multiplication (VMM). MACC-SRAM also integrates 128 stepwise-charging and dis- charging input drivers (SCD-IDRs) to efficiently convert the digital codes of the input activati