JSSC 2024第6期Other65nm

V oltage Level Detection for Near-VTH Computing

提出了一种无毛刺的低压电压检测器，适用于近阈值计算，检测电压低至385mV，功耗217nW，延迟10µs。

385 mV, 217 nW, 10 µs, 6900 µm², 105 µW/°C, 8 mV

电压检测器近阈值计算低功耗无毛刺确定性延迟

▸创新点1：无毛刺设计通过引入确定性延迟和优化的内部节点控制，有效消除了传统电压电平检测器中的竞争条件，确保在385 mV超低电压下仍能稳定工作，解决了近阈值计算中的误触发问题。

▸创新点2：确定性延迟插入技术采用精准时序调控电路，在10 µs延迟内实现快速电压检测，同时将功耗降低至217 nW，显著提升了近阈值计算系统的响应速度和能效比。

▸创新点3：低压电路设计通过65 nm CMOS工艺实现6900 µm²的小面积布局，支持385 mV超低供电电压检测，温度漂移仅105 µW/◦C，32个单元测试显示8 mV的σ变异，为近阈值计算提供了高可靠性硬件基础。

▸创新点4：系统级集成创新将VLD与近阈值计算单元深度融合，通过协同优化电源管理和计算时序，实现了在快速供电变化环境下的无缝切换，扩展了低功耗物联网设备的应用场景。

Abstract

V oltage level detectors (VLD) are used to monitor the supply voltage in integrated circuits (ICs) to determine when the system can initiate computation. The VLD must detect its own supply voltage, which is more challenging for low-voltage applications such as near- VTH computing (NVTC), which also requires low latency and rapid supply changes; furthermore, internal races in the VLD may cause false indications or glitches in the system and should be prevented by design. This work presents a glitch-free VLD that can detect supplies as low as 385 mV at a power of 217 nW and a measured latency of 10 µs. This was achieved by inserting a deterministic delay into one of the internal nodes, as well as low-voltage circuitry. The circuit is fabricated in a 65 nm CMOS process and occupies a footprint of 6900 µm2 with a measured temperature drift of 105 µW/◦C and a sigma variation of 8 mV across 32 units. These characteristics make the circuit attractive for the near-threshold computing segment.