JSSC 2024第7期Data Converters28nmSAR ADC

A 0004-mm 2 200-MSs Pipelined SAR ADC With kTC Noise Cancellation and Robust Rin

一种采用kT/C噪声消除技术和鲁棒输入的小面积高速SAR ADC

28nm CMOS, 13-bit, 200MS/s, 0.004mm², 1.3mW

流水线SAR ADCkT/C噪声消除环形放大器电流偏置小面积设计

▸采用分体电容的电流偏置方案增强环形放大器的PVT鲁棒性

▸无缝集成kT/C噪声消除技术突破输入采样噪声极限

▸仅需128fF单端输入采样电容实现高能效转换

Abstract

This article presents a compact 13-bit 200-MS/s pipelined successive-approximation register (SAR) analog-to- digital converter (ADC) with a robust current-biased ring amplifier (ring-amp) and kT/C noise cancellation. The proposed current-biasing scheme using split capacitors significantly enhances the PVT robustness of the ring-amp. With additional split capacitors used for current-biasing, the kT/C noise cancellation technique can be seamlessly implemented in this architecture. With kT/C noise