← 返回 JSSC 论文列表JSSC 2024第7期RF & Wireless5-nm FinFETDACEqualizer
A 116-Gbs PAM4 09-pJb Transmitter With Eight-Tap FFE in 5-nm FinFET Yevgeny Pere
一篇关于116-Gb/s PAM4电压模式发射器的IEEE JSSC论文，采用5-nm FinFET工艺实现高效能传输。
116-Gb/s PAM4, 0.9 pJ/bit, 0.082 mm²面积
PAM4发射器前馈均衡器5-nm FinFET高效能
▸采用8-tap前馈均衡器(FFE)的4:1多路复用7位DAC驱动器
▸数据路径和时钟路径架构创新，支持高达14.5 GHz操作
▸低电压供电(0.75 V)下的高效能设计
Abstract
This article presents a 116-Gb/s PAM4 voltage-
mode (VM) transmitter (TX). The TX includes a 4:1-multiplexed
7-bit digital-to-analog converter (DAC) driver with an eight-
tap feedforward equalizer (FFE). A high energy efficiency of
0.9 pJ/bit was achieved by novel data and clock path architectures
that operate at up to 14.5 GHz. In the data path, the serializer
is based mainly on MUXes that are biased in an unregulated
low voltage supply of 0.75 V . Since high-quality clocks are not
needed in th