A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process

Abstract

Direct-digital frequency synthesizers (DDSs) are highly attractive in wireless communications because of their fast frequency hopping characteristics. Generally, DDSs adopt trun- cation and thermometer decoding for high-frequency resolution and monotonicity, respectively. However, the truncation causes poor spectral purity due to periodical errors in phase accumula- tion. Also, the thermometer decoding scheme of digital-to-analog converter (DAC) requires many current sources, which creates large parasitic components and nonlinearity. This article presents several techniques for addressing the above challenges. First, a fixed-weight decoder (FWD) with an auxiliary DAC is proposed to remove the truncation spur in the phase accumulation. Since FWD controls the amplitude regardless of the phase, it removes the periodic errors without significant power increment. Second, the proposed tristate decoding scheme reduces the number of current sources to reduce timing mismatches and capacitances. Finally, a fine current source reusing technique is developed to reduce the number of current sources and power consumption. The proposed DDS was fabricated in a 65-nm CMOS technology. The worst spurious-free dynamic range (SFDR) is 57.35 dBc at 2.5 GHz with a power consumption of 104 mW. The measured figure of merit is 18 124 GHz ·2(SFDR/6)/W.