← 返回 JSSC 论文列表JSSC 2024第7期RF & Wireless65nmClock Generation
A 25-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequen
提出了一种基于DAC的直接数字频率合成器，通过固定权重解码器和三态解码方案提升性能。
最差无杂散动态范围（SFDR）57.35 dBc @2.5 GHz，功耗104 mW
直接数字频率合成器动态范围电流源复用相位累积误差三态解码
▸固定权重解码器（FWD）与辅助DAC消除相位累积误差
▸三态解码方案减少电流源数量
▸精细电流源复用技术降低功耗
Abstract
Direct-digital frequency synthesizers (DDSs) are
highly attractive in wireless communications because of their fast
frequency hopping characteristics. Generally, DDSs adopt trun-
cation and thermometer decoding for high-frequency resolution
and monotonicity, respectively. However, the truncation causes
poor spectral purity due to periodical errors in phase accumula-
tion. Also, the thermometer decoding scheme of digital-to-analog
converter (DAC) requires many current sources, which creates
large