JSSC 2024第7期Data ConvertersSAR ADCNeural Network Accelerator

A 511-µW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique Hao-Hsuan Chang , Ci-Ren Chen , and Tai-Cheng Lee

提出了一种混合两级ADC，结合SAR ADC和ISDM ADC，提升SNDR和功率效率。

370kHz频率，185kHz带宽，511µW功耗，89.3dB SNDR

混合ADCSAR ADCISDM ADC噪声整形功率效率

▸创新点1：异步操作（方法创新）。该ADC采用异步操作模式，避免了传统同步时钟的时序限制，显著提高了转换速度和功耗效率，适用于低功耗应用场景。

▸创新点2：时间域噪声切片技术（TDNS，方法创新）。通过时间域噪声切片技术，重构每个周期的噪声和功率权重，优化了FoM，提升了ADC的整体性能。

▸创新点3：噪声整形技术（电路创新）。采用噪声整形技术抑制比较器放大器（CB amplifier）的噪声，进一步提高了信噪比和失真比（SNDR），达到89.3 dB。

▸创新点4：混合两级架构（系统创新）。结合粗精两级ADC，粗级3.3-V SAR ADC提升最大输入幅度，精细级1.8-V CB ISDM ADC优化噪声和功耗，实现了511 µW的低功耗和高动态范围（94.5 dB）。

Abstract

This work proposes a hybrid two-stage analog- to-digital converter (ADC) consisting of a coarse 3.3-V successive-approximation register (SAR) ADC and a fine 1.8-V comparator-based (CB) incremental 16 modulator (ISDM) ADC. The coarse ADC boosts the maximum input amplitude to improve signal-to-noise and distortion ratio (SNDR), and the fine ISDM ADC adopts an asynchronous operation and a time-domain noise-slicing (TDNS) technique to improve power efficiency and conversion speed. Using the unequal data weighting of ISDM and the noise–slope relationship of the CB amplifier, the TDNS technique reconstructs the noise and power weighting of each cycle to optimize the figure of merit (FoM). Furthermore, the noise of the CB amplifier is suppressed by the noise-shaping (NS) technique. The ADC operates at a 370-kHz frequency and achieves 94.5/89.3-dB dynamic range (DR)/SNDR in a 185-kHz bandwidth (BW). It achieves a Schreier FoM of 174.88 dB and consumes 511 µW.