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JSSC 2024第7期RF & Wireless65nmPLL

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedb

提出一种基于谐波混频器双反馈和分频反馈的分数N环PLL,实现低相位噪声和抖动。
65-nm CMOS, −229.4-dB jitter-power FoM, −49-dBc worst-case fractional spurs, 40-MHz reference
分数N环PLL谐波混频器双反馈分频反馈低相位噪声
克服传统双反馈PLL的噪声整形频率限制
解决稳定性和噪声开销问题
实现宽环路带宽和有效量化噪声抑制
Abstract
A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback architecture is presented in this article. The proposed architecture not only overcomes the noise shaping frequency limitation seen in a conventional dual-feedback PLL, but also solves stability and noise overhead issues that were present in the prior art. Due to the wide loop bandwidth that can be achieved because of the effect