Abstract
This work demonstrates two integrated 256-kb in-memory computing (IMC) macros based on foundry MRAM, implemented in a 22-nm fully depleted silicon on insulator (FD- SOI) CMOS process. Embedded non-volatile memory (eNVM), including MRAM, resistive RAM (ReRAM), and phase-change memory (PCM), is an emerging class of technologies that have drawn interest for IMC due to their potential to achieve high den- sity with advanced-node scaling as well as low-power always-on/ duty-cycled operation. However, the typically low bit-cell signals (i.e., resistance contrast) necessitate high-sensitivity readout cir- cuitry, particularly with the high levels of IMC row parallelism desired for maximizing energy efficiency and compute density. This work analyzes power supply and coupling noise, which arises and poses a primary limitation in recent high-sensitivity, high-efficiency architectures, preventing their integration and scale-up in systems on chip (SoCs). To address this, a differential readout architecture is demonstrated, which retains the previous efficiency and density while overcoming power-supply interfer- ence and coupling by over 100 × between the many parallel readout channels. The architecture is based on conductance- to-current ( G-to-I) conversion, column-weighted combining for analog-to-digital converter (ADC) sharing, and 6-b digitiza- tion via a successive-approximation current-to-digital converter (IDC). Enabling fully parallel operation across 128–512 rows and 512 columns