A Highly Linear and Efficient V -Band CMOS Power Amplifier Using Hybrid NMOS/PMOS for Double Nonlinearity Cancellation With Four-Way Distributed-Active-Transformer Tso-Wei Li

Abstract

This article presents a V-band (i.e., 47-75 GHz) differential four-way distributed-active-transformer (DAT) power amplifier (PA), which uses hybrid NMOS/PMOS for double nonlinearity cancellation to improve the linearity with minimal impact on the overall PA efficiency. Implemented in the 45-nm CMOS silicon-on-insulator (SOI) process, the proposed PA con- sists of three stages, pre-driver, driver, and PA stages, to deliver the desired gain at the V-band. The PA stage includes both NMOS and PMOS transistors, while the driver stage adopts PMOS and the pre-driver stage uses NMOS transistors. This mixed NMOS/PMOS scheme provides a high-order nonlinearity cancellation, substantially improving the PA linearity, and opti- mizes its performance. An ultra-compact differential four-way series–parallel DAT-based power combiner is used to provide the optimum load (R opt) to the mixed NMOS/PMOS PA. This proposed PA output matching network/power combiner only occupies one transformer footprint, resulting in a reduced chip area and design complexity. The PA achieves peak power-added- efficiency (PAE) of 35.4%, saturation power (P sat) of 16.3 dBm, and AM–PM distortion <2◦ (at output 1-dB compression point– 13.5 dBm) in 50.4-58 GHz. The AM–PM distortion drops <0.5◦ at 55 GHz. The PA exhibits an average PAE (PAE avg) of 15.6% and rms error vector magnitude (EVM) <−25 dB when transmitting a 64-QAM modulated signal with 9.5 dBm average output power (P avg) at 0.5 GSym/s. The EVM remains better t