← 返回 JSSC 论文列表JSSC 2024第7期Power Management40nmEmerging Memory
EMBER Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digi
EMBER提出高效多比特RRAM宏设计,优化读写电路并提升存储密度与可靠性。
100 MHz, 64k×48=3M cells
多比特RRAM存储密度读写电路优化共模泄放片上控制器
▸通过约束优化驱动器和传输门晶体管尺寸实现读写电路紧凑化
▸引入共模泄放电导技术,将低电导单元的读取稳定时间减少11.35倍
▸采用可配置的片上读写控制器解决可靠性和写入速度问题
Abstract
Designing compact and energy-efficient resistive
RAM (RRAM) macros is challenging due to: 1) large read/write
circuits that decrease storage density; 2) low-conductance cells
that increase read latency; and 3) the pronounced effects of
routing parasitics on high-conductance cell read energy. Multiple-
bits-per-cell RRAM can boost storage density but has further
challenges resulting from reliability problems due to conductance
relaxation and slow write due to narrow conductance levels.
This work