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Guest Editorial IEEE 2023 European Solid-State Circuits Conference W ELCOME to t
IEEE JSSC期刊介绍2023年欧洲固态电路会议精选论文，涵盖PLL、电压模式驱动器、声学传感、3D EIT成像系统和节能技术等创新研究。
40-Gb/s NRZ, 50-Gb/s PAM4, 1.4 dBm, 0.82 pJ/b
PLL电压模式驱动器MEMS3D EIT成像节能技术
▸多参考PLL实现极低抖动
▸级联电压模式驱动器提高功率效率
▸MEMS与光学转换技术结合降低系统噪声
Abstract
D -STATE CIRCUITS , featuring a curated
selection of papers from the European Solid-State Circuits
Conference (ESSCIRC) held in Lisbon, Portugal, September
11–14, 2023. As Guest Editors, we are delighted to present
these papers and hope you find inspiration in these outstanding
works.
In [A1], Liu et al. explore the role of the reference in
minimizing phase-locked loop (PLL) phase noise. They use
this to realize a PLL that uses multiple references to achieve
extremely low jitter.
The paper [A2]