JSSC 2024第7期Memory16nmEmerging Memory

Siracusa A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neura

16nm异构RISC-V SoC Siracusa，集成MRAM神经引擎，提升XR能效。

65.2 GOp/s/mm², 8.84 TOp/J

扩展现实RISC-VMRAM神经引擎能效优化

▸异构SoC集成RISC-V DSP核心与数字神经引擎N-EUREKA

▸采用At-Memory技术紧密集成MRAM非易失存储器

▸支持复杂异构应用，结合机器学习与传统信号处理

Abstract

Extended reality (XR) applications are machine learning (ML)-intensive, featuring deep neural networks (DNNs) with millions of weights, tightly latency-bound (10–20 ms end-to- end), and power-constrained (low tens of mW average power). While ML performance and efficiency can be achieved by introducing neural engines within low-power systems-on-chip (SoCs), system-level power for nontrivial DNNs depends strongly on the energy of non-volatile memory (NVM) access for network weights. This work intr