← 返回 JSSC 论文列表JSSC 2024第8期Power Management40nm CMOSPLL
A Fractional- N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD Ga
提出一种3.3-4.5 GHz分数-N采样锁相环，结合恒定斜率DTC和采样PD，降低噪声和非线性。
203 fs rms抖动, 2.4 mW功耗, FoM -250 dB
分数-N采样锁相环恒定斜率DTC采样相位检测器多模分频器量化噪声消除
▸合并恒定斜率DTC和采样PD
▸改进多模分频器减少线性范围需求
▸单斜坡生成实现相位误差检测和量化噪声消除
Abstract
This article presents a 3.3–4.5-GHz fractional- N
analog sampling phase-locked loop (SPLL). A merged constant-
slope digital-to-time converter and sampling phase detector
(CSDTC-SPD) allows phase error detection as well as quan-
tization noise (QN) cancellation in a single ramp generation,
which reduces the source of noise and nonlinearity. A modified
multimodulus divider (MMDIV) with two phase retimers reduces
the required CSDTC-SPD linear range and decreases the noise
from the CSDTC-SPD. To ve