JSSC 2024第8期Power Management65nmNeural Network Accelerator

A High-Efficiency 4068-MHz Single-Stage Dual-Output Regulating Rectifier With ZV

一种高效40.68MHz单级双输出调节整流器，采用ZV开关控制。

65nm CMOS, 2.2V/1.1V双输出, 60.5mW, 90.1%峰值效率

高频整流器双输出零电压开关有源二极管40.68MHz

▸创新点1：新型三有源二极管整流拓扑结构，通过仅使用三个有源二极管实现双输出，显著简化了传统双输出整流器的电路复杂度，同时提高了功率转换效率（峰值效率达90.1%）

▸创新点2：零电压开关(ZVS)导通控制技术，针对40.68MHz高频输入电压优化，有效降低二极管导通损耗，提升整体系统效率，尤其在高频工况下表现优异

▸创新点3：同步PFM双输出调节控制方案，实现了两个输出电压（2.2V和1.1V）的快速负载瞬态响应，且输出交叉调节效应几乎不可察觉

▸创新点4：支持40.68MHz最高谐振频率输入，使接收端(RX)线圈尺寸减小至少4倍，为小型化无线供电系统提供了创新解决方案

Abstract

This article presents a 40.68-MHz single-stage dual- output regulating (SSDOR) rectifier, which has a new rectifier topology with only three active diodes for producing two outputs. Zero-voltage switching (ZVS) turn-on control for each active diode is developed to minimize converter power loss when rectifying 40.68-MHz input ac voltage. Synchronous PFM control is also proposed to regulate both outputs and provides fast load transient responses. Implemented in a 65-nm CMOS process with 2.5-V I/O