A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerato

Abstract

This work presents a digital hardware accelerator with compute-near-memory to solve 2-D and 3-D partial dif- ferential equations (PDEs) using the finite difference method (FDM). The proposed hardware accelerator is reconfigured to solve 2-D/3-D Laplace and Poisson equations, and it scales to solve larger 2-D problems with no additional overhead. The reconfigurable and scalable architecture is implemented by building a 16 × 16 near-memory bit-serial processing element (PE) array and four 16× boun