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JSSC 2024第8期RF & Wireless65nm

An IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS Yunzhao Nie

提出一种基于正交混合相关法的低功耗超宽带接收机架构,采用模拟相关和时间交错采样技术。
65nm CMOS, 17.3mW, -88dBm灵敏度, 1.9cm测距误差
超宽带接收机正交混合相关低功耗模拟相关器时间交错采样
创新点1:正交混合相关法降低数字相关功耗(方法创新)。通过引入正交混合相关(QHC)方法,将传统UWB接收器中的数字相关操作转移到模拟域,显著降低了数字相关相关的功耗,提升了能效。
创新点2:两步同步与数字辅助路径(系统创新)。采用两步同步机制,结合数字辅助路径,实现了低功耗的同步和解调,同时提高了系统的同步精度和鲁棒性。
创新点3:三元模拟相关器用于噪声抑制(电路创新)。设计了三元模拟相关器,有效抑制了噪声干扰,提高了信号处理的质量和计算精度,特别是在低信噪比环境下表现优异。
创新点4:时间交错采样方法(系统创新)。引入时间交错(TI)采样技术,进一步降低了功耗并提高了采样效率,支持高符号率(0.98/7.8 Mbaud/s)下的稳定工作。
Abstract
This article presents a coherent ultra-wideband (UWB) receiver architecture based on a quadrature hybrid correlation (QHC) method that significantly reduces the digital-correlation-relevant power in the conventional standard-compliant UWB receiver. The proposed QHC receiver front end employs analog correlation, two-step synchronization with a digital-assisted path, and time-interleaved (TI) sampling methods for low-power synchronization and demodulation. A code-mismatch-evaluation method is adopted to achieve the time-of-arrival (ToA) function. In addition, a ternary analog correlator is designed for noise mitigation and high- quality computing. A prototype UWB receiver covering an 8-GHz channel is implemented in 65-nm CMOS. The receiver supports preamble, scrambled timestamp sequence (STS), and burst position modulation (BPM) with a symbol rate of 0.98/7.8 Mbaud/s. With a duty-cycled operation, the receiver consumes 17.3 mW at 0.98 Mbaud/s with a sensitivity of −88 dBm at a bit-error rate (BER) of 10 −3 during payload. The blocker tolerance is −24 dBm. In the STS field, the receiver achieves an rms ranging error of 1.9 cm.