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JSSC 2024第9期Clocking & PLLs65nmVCOClock Generation

A 6 to 12-GHz Fractional- N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

一款6至12GHz分数N频率合成器,采用数字技术解决反馈分频器延迟问题。
65nm CMOS, 1V, 66mW, 280kHz带宽, 400-500fs抖动
频率合成器分数NVCO相位噪声CMOS
采用电感模式切换和电容切换的VCO设计
新型数字技术减少模数依赖延迟
周期性误差转换为参考频率一半的滤波处理
Abstract
This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to con- ventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). Modulus- dependent delay (MDD) of the feedback divider increases jitter in fractional- N mode. The delay change can exceed 100 ps when the number of stages in the divider chain changes. A new digital technique, which can be realized with minor modifications to the conventional digital delta-sigma modulator (DDSM), is imple- mented to overcome this effect. The delay change is turned into a periodic error at half the reference frequency that is then filtered by the loop filter. The prototype synthesizer in 65-nm CMOS occupies 0.54 mm 2 and consumes 66 mW at the highest frequency from a 1-V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400, 300, and 500 fs in the 6 to 8-GHz, 8 to 10-GHz, and 10 to 12-GHz ranges, respectively. The worst case reference spurs are below −60 dBc and the fractional spurs are below −31 dBc.