← 返回 JSSC 论文列表JSSC 2024第9期RF & Wireless65nmVCOEqualizer
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for
提出一种单端阻抗匹配发射器,采用环形振荡器时域ZQ校准,实现低误码率和高效能。
65nm CMOS, 12 Gb/s, 1.145 pJ/bit, FoM 0.11 pJ/bit/(dB/pin)
单端发射器阻抗匹配ZQ校准相位均衡低功耗
▸创新点1:单环形振荡器时域ZQ校准方法创新,采用增益控制环形振荡器和迟滞强制技术,消除偏移,实现最大误差率1.5%和平均误差率0.7%,显著提升校准精度。
▸创新点2:相位均衡方法电路创新,通过最小化硬件复杂度实现前导码间干扰补偿,不影响阻抗匹配,降低设计复杂度和功耗,提升系统稳定性。
▸创新点3:系统级创新,结合ZQ校准和相位均衡,在65nm CMOS工艺下实现0.074mm²的发射器面积和1.145pJ/bit的能效,FoM达0.11pJ/bit/(dB/pin)。
▸创新点4:硬件优化创新,通过精简ZQ校准电路结构,仅占用0.041mm²面积,在12Gb/s速率下保持高能效和小尺寸。
Abstract
The proposed single-ended transmitter for memory interfaces is an impedance-matched transmitter that utilizes a single ring-oscillator-based time-domain ZQ calibration. This ZQ calibration technique eliminates the offsets by using a gain-controlled ring oscillator with late-case forcing, resulting in low maximum/average error rates. The transmitter incorporates a phase equalization method to compensate for pre-cursor inter-symbol interference (ISI) without affecting the impedance matching achieved by ZQ calibration. This phase equalization is implemented by minimizing hardware to overcome the design complexity of conventional phase equalization and reduce power consumption. The prototype chip is fabricated in the 65-nm CMOS process. The transmitter and the ZQ calibration scheme occupy an area of 0.074 and 0.041 mm 2, respectively. The proposed ZQ calibration achieves a maximum error rate of 1.5% and an average error rate of 0.7%. In addition, the transmitter achieves an energy efficiency of 1.145 pJ/bit and an FoM of 0.11 pJ/bit/(dB/pin) at 12 Gb/s.