Analysis and Design of a 10.4-ENOB 0.92–5.38-µW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications Jonah Van Assche , Student Member , IEEE, and

Abstract

Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power con- sumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/or processing power, mak- ing them well-suited for low-power edge applications. Current implementations are, however, limited in performance and power efficiency. Due to the asynchronous output stream, it is also difficult to interface such LCADCs with (conventional) clocked digital processing circuits/transmitters. This article introduces a new LCADC topology, with clocked comparators but with an adaptive clocking scheme. It has a low power consumption and can seamlessly be integrated with any type of process- ing/transmission circuit. This article first analyzes the major bottleneck to the power consumption of the classical continuous- time (CT) LCADCs. A new, more power-efficient topology with clocked comparators is then introduced. Thanks to the adaptive clocking algorithm, the power consumption scales with the signal activity. The discrete-time (DT) topology can achieve a 10×– 100× lower comparator power depending on the signal activity. A prototype IC with an 8-bit 15-kHz BW LCADC is implemented in a 40-nm CMOS technology. Measurement results show that the ADC has an activity-based power consumption from 0.92 µW for an ECG signal to 5.38 µW fo