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JSSC 2024第9期Digital Circuits65nm

INTIACC: A Programmable Floating- Point Accelerator for Partial Differential Equations Paul

INTIACC是一种可编程浮点加速器,用于高精度求解多种偏微分方程。
65nm CMOS, 1V, 570MHz, 9.12GFLOPS
浮点加速器偏微分方程可编程数值积分高精度
16个本地互连的可编程RISC处理单元
新型慢全局快局部时钟方案
支持高阶积分方法和非线性函数评估
Abstract
This article presents a 32-bit floating-point (FP32) programmable accelerator for solving a wide range of partial differential equations (PDEs) based on numerical integration methods. Compared to prior works that have fixed-point systems and are only applicable to specific types of PDEs, our proposed, integration accelerator for PDEs, named INTIACC, accelerator consists of 16 locally interconnected processing elements (PEs) where each PE is a fully programmable reduced instruction set computer (RISC) processor with an FP32 arithmetic logic unit (FP32 ALU) and a custom-designed instruction set architecture (ISA). These features enable INTIACC to generate solutions with high precision and a wide dynamic range and also allow users to implement different numerical algorithms to perform high-order integration methods and to evaluate nonlinear functions. In addi- tion, we create a novel slow-global-fast-local clocking scheme in which PEs operate asynchronously with each other most of the time. We prototype the INTIACC test chip in 65 nm, with a core area of 0.975 mm 2. Running at an average local clock frequency of 570 MHz at 1 V , it offers a single-precision computation throughput of 9.12 GFLOPS. Testing results show that with a similar energy-delay product, INTIACC is up to 40 × faster than the prior state-of-the-art PDE solver.