A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses Xiang’ao Qi

Abstract

Spiking neural networks (SNNs) are garnering increasing attention due to their potential to explore the com- plexities of the human brain and utilize its capabilities. The broad spectrum of applications presents challenges in designing SNN-based neuromorphic systems First, the SNN uses complex models [e.g., Izhikevich (IZ)] for brain simulations and simpler models [e.g., Leaky Integrate and Fire (LIF)] for efficient machine learning, presenting a challenge in realizing neuron circuits supporting diverse applications. Second, densely connected net- works with uneven spike distributions lead to Network-on-Chip (NoC) congestion and delays, complicating the optimization of throughput/area. An SNN accelerator, featuring 128/256 recon- figurable neurons and asynchronous fully connected synapses, has been developed to address these challenges. The reconfigurable neuron circuit is capable of switching between the LIF neuron model and the IZ neuron model. The proposed chip achieves a peak power efficiency of 5.37 TSOPs/W and throughput of 25.6 MSOPs/s. The near-threshold operation of neurons, in con- junction with asynchronous fully connected synapse, reduces energy by 9.42× to a 9.27 pJ/pixel in image feature extraction.