JSSC 2024第10期RF & Wireless10nmDRAM

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications Hyun-A Ahn

提出第四代10nm 16Gb LPDDR5x DRAM的I/O电路和控制方法，实现8.5Gbps低功耗运行。

8.5Gbps, 0.66UI Tx眼宽, 0.57UI Rx眼宽, 功耗降低20%

LPDDR5x低功耗信号完整性电源完整性SDRAM

▸创新点1：自预加重堆叠驱动器（电路创新）。通过引入自预加重技术，显著改善了发射端（Tx）的信号完整性（SI），在8.5 Gbps速率下实现了0.66 UI的眼图宽度，提升了高速数据传输的可靠性。

▸创新点2：电源电压不敏感数据接收器（电路创新）。设计了一种对电源电压变化不敏感的数据接收器（Rx），增强了接收端的信号完整性（SI），在8.5 Gbps速率下实现了0.57 UI的眼图宽度，提高了系统鲁棒性。

▸创新点3：优化的WCK时钟树（系统创新）。通过优化写时钟（WCK）路径中的时钟树设计，减少了时钟抖动和功耗，同时提升了时序精度，使整体功耗降低了20.0%，显著提高了能效。

▸创新点4：集成低功耗设计（系统创新）。结合上述创新点，整体实现了低功耗8.5 Gbps操作，显著降低了功耗，同时保持了高性能和高可靠性，适用于移动设备等低功耗场景。

Abstract

For low-power 8.5-Gbps operation, 4th-generation 10-nm 16-Gb LPDDR5x DRAM I/O circuits and control methods are proposed in this article. The proposed I/O improves signal integrity (SI) and power integrity (PI) by using a self-pre- emphasized stacked driver in transmitter (Tx), a supply voltage insensitive data receiver (Rx), and an optimized clock tree in write clock (WCK) clock paths. The measured eye widths of Tx and Rx, which are the indicators of the SI/PI, are 0.66 unit interval (UI) and 0.57 UI at 8.5 Gbps, respectively. Also, the measured power consumption is reduced by 20.0% compared to the previous LPDDR5 SDRAM product.