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A 28-nm 36 Kb SRAM CIM Engine With 0173 µm2 4T1T Cell and Self-Load-0 Weight Upd
28纳米36Kb SRAM存内计算引擎，采用0.173µm² 4T1T单元，支持自加载0权重更新。
28nm CMOS, 263.1/412.1 TOPS/W (FF/BP), 2.5/4.9 TOPS/mm² (FF/BP)
存内计算SRAM神经网络训练能效优化权重更新
▸4T1T SRAM单元实现非破坏性读取和最小面积
▸共享路径双模读取减少电路开销
▸IR-drop感知自适应钳位器提升电压精度
Abstract
Computing-in-memory (CIM) promises high energy
efficiency (EE) and performance in accelerating the feed-forward
(FF) and back-propagation (BP) processes of deep neural net-
works (DNNs) with less data movement and high parallelism.
However, challenges still lie in large memory cells, network
mapping, and IR-drop variation to realize efficient CIM imple-
mentation. In this work, a 28-nm 36 Kb static random-access
memory (SRAM) CIM engine with nondestructive-read (NDR)
cell and weight update energ