JSSC 2024第10期Power ManagementLDO

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3 Jinook Jung , Jun-Han Choi , Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong

提出基于翻转电压跟随器的快速LDO，4ns建立时间，适用于HBM3内存，减少电源抖动。

4ns建立时间，40mV下冲，46mV过冲，20pF负载电容，0.0061mm²面积

低dropout稳压器翻转电压跟随器带宽扩展HBM3电源抖动

▸创新点1：翻转电压跟随器（FVF）设计方法创新，通过优化传统LDO结构实现4 ns超快建立时间，解决了HBM3应用中电源抖动（PSIJ）的关键问题，显著提升高频稳定性。

▸创新点2：带宽扩展技术创新，结合有源电感与自适应偏置策略，动态提升环路带宽至GHz级别，使20 pF负载下仅产生40 mV下冲/46 mV过冲，优于同类模拟方案。

▸创新点3：两步数字方法创新，通过数字辅助校准替代传统全模拟控制，降低工艺偏差影响，将HBM3的DQS时钟眼宽从303 mUI提升至424 mUI，量化验证系统级性能优势。

▸创新点4：微型化面积优化（0.0061 mm²），采用紧凑型布局技术，在维持高频性能的同时实现芯片面积最小化，为高密度集成HPC场景提供可行性。

Abstract

This article introduces a novel low-dropout (LDO) regulator based on a flipped-voltage follower (FVF) design, achieving a rapid 4 ns settling time. Tailored for high band- width memory generation 3 (HBM3) applications, it minimizes power supply-induced jitter (PSIJ), crucial in high-performance computing (HPC). The design integrates advanced bandwidth extension techniques, including active inductors and self-adaptive bias strategy. Additionally, a two-step digital approach signifi- cantly enhances performance over analog solutions. The proto- type, occupying only 0.0061 mm 2, achieves 40 mV undershoot and 46 mV overshoot voltage with 20 pF load capacitance, significantly enhancing the eye width of the write data strobe (DQS) clock in HBM3 to 424 mUI from 303 mUI, demonstrating its efficacy in HPC environments.