A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier

Abstract

This article presents an energy-efficient and easily adjustable floating-inverter amplifier (FIA), named the cyclically charged FIA (CC-FIA). Its bias point can be adjusted to a stable operating region by reusing multiple switched capacitors, which allows for enhancing current efficiency (gm/ID) by setting its bias point in the near- or sub-threshold region. Easy reconfiguration of bias points enables maximizing amplifier energy efficiency across different sampling frequencies for event-driven ADC. The proposed FIA also features a stable and easily tuned open-loop gain, eliminating stability issues in closed-loop configurations and further enhancing its energy efficiency. It occupies a significantly smaller area than conventional FIAs because each reservoir capacitor pumps charge to the amplifier multiple times. The CC-FIA is implemented in a pipelined-SAR ADC as an open-loop residue amplifier and fabricated in a 65-nm CMOS process. The prototype ADC achieves an SNDR of 74.0 dB and an SFDR of 85.5 dB at a sampling frequency of 2 MS/s. The ADC consumes 72.3 µW at a supply voltage of 1.2 V , resulting in a Schreier figure-of-merit of 175.4 dB.