A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS

Abstract

This article introduces a highly integrated V-band frequency-modulated-continuous-wave (FMCW) radar transceiver (TRX) in 40-nm bulk CMOS. It incorporates two identical transmitter (TX) and receiver (RX) channels, enabling not only traditional forward sensing but also full-360 ◦ detection. The FMCW synthesizer is based on a cascaded-phase-locked- loop (PLL) topology, enhancing chirp quality while reducing the necessity for complex off-chip components. Additionally, it generates extra clocks to ensure synchronized operation for the entire radar system. A proportional-to-absolute-temperature (PTAT)-enhanced temperature compensation (TC) technique is proposed to improve the temperature robustness at V-band. The impacts of clock synchronization and temperature insen- sitivity of the TRX on FMCW radar systems are also analyzed. For broadband, high-linearity, and low-noise operation within limited stages, RF front-ends are carefully designed, with the optimization strategy elaborated. Fabricated in a fan-out wafer- level chip-scale packaging (WLCSP), this TRX achieves a 3-dB bandwidth ranging from 54 to 69 GHz. The RX features a 67-dB tuning range of the conversion gain (CG) and a 10-dB noise figure (NF). The PSAT of TX is 12.8 dBm. The PTAT-enhanced TC effectively minimizes variations in CG, NF, and PSAT, maintaining less than 2.1-, 2.9-, and 2.5-dB changes, respectively, from −55 ◦C to 105 ◦C. The FMCW generator achieves a chirp rate of 468.5 MHz/µs with a bandwidth of 7.2 GHz, de