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JSSC 2024第12期Clocking & PLLs28nmPLLRadar

A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars

基于数字PLL的10GHz啁啾信号发生器,采用新型数字预失真算法优化DCO非线性调谐曲线。
28nm CMOS, 21mW功耗, 680MHz/µs斜率, 680MHz带宽, 150kHz RMS频率误差, -116.5dBc/Hz@1MHz相位噪声
啁啾信号发生器数字锁相环数字预失真频率调制连续波雷达数控振荡器
采用两点调制技术的数字PLL架构
针对DCO非线性调谐曲线的非均匀分段抛物线数字预失真算法
自适应非均匀分布断点自动定位技术
Abstract
This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/µs and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.