A 121.7-dB DR and −109.0-dB THD +N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

Abstract

The dynamic range (DR) of digital-input closed- loop class-D amplifiers (CDAs) is typically limited by the noise introduced by their resistive DAC (RDAC) or current-steering DAC (IDAC). It could be improved by using tri-level cells in the IDAC, but this has not yet been realized in high-voltage (HV) CDAs due to the large difference in the common-mode levels between the DAC and the CDA. This article describes an HV CDA directly driven by an HV IDAC. By using the same output common mode for the digital-to-analog converter (DAC) and CDA, the noise penalty associated with shifting the common mode is avoided. To address the distortion due to mismatch and intersymbol interference (ISI) in the IDAC, a transition- rate-balanced bidirectional real-time dynamic element matching (RTDEM) technique is also introduced. Fabricated in a 180-nm BCD process, the CDA prototype achieves a DR of 121.7 dB and a peak THD +N of −104.0 and −109.0 dB for 1- and 6-kHz inputs, respectively. It can deliver a maximum of 14 W into an 8- load with a power efficiency of 90%.