JSSC 2024第12期Clocking & PLLs28nmPLL

A 232-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reu

一种基于功能复用VCO缓冲器的低抖动快速锁定亚采样锁相环，适用于毫米波频率合成。

28nm CMOS, 0.065mm², 26GHz, 48.3fs rms jitter, 19.1mW, -66dBc ref. spur, 55 ref. cycles locking time

亚采样锁相环毫米波低抖动快速锁定功能复用

▸功能复用VCO缓冲器消除晶体管噪声和电容负载

▸低功耗快速频率锁定环采用相位对齐器

▸粗-细时间数字转换器加速开关电容控制字搜索

Abstract

This article presents a type-II sub-sampling phase- locked loop (SSPLL) that achieves low jitter, low spur, and sub-µs locking time when synthesizing millimeter-wave (mm-wave) fre- quencies. The proposed function-reused (FR) voltage-controlled oscillator (VCO)-buffer eliminates the noise and capacitive load- ing from the transistors in the buffer, improving the jitter and reference (ref.) spur of the SSPLL simultaneously. It also eliminates the inductor typically employed in the high-frequency b