A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120 × Multiplying Factor and 92.3-fs RMS Jitter Including

Abstract

This article presents a subharmonic injection-locked clock multiplier (SILCM) with low rms jitter and low refer- ence spur. To improve rms jitter while suppressing reference spur, reference injection is performed using two operations, reset and recovery. During the reset operation, outputs of voltage-controlled oscillator (VCO) are shorted to each other to remove accumulated jitter. During the recovery operation, the distorted VCO waveform caused by reset operation is restored. To minimize reference spur, calibration loops are used to control VCO frequency, recovery levels, and recovery timing. Furthermore, internal offset of the calibration circuit is also removed. Implemented in 28-nm CMOS, the proposed SILCM achieves a 67.7-fs rms jitter and a reference spur of −56.6 dBc at 7.5 GHz with 62.5-MHz reference, while consuming 2.33 mW. It achieves a state-of-the-art figure-of-merit (FoM J+spur,REF) of −259.1 dB, which includes reference frequency and spur.