← 返回 JSSC 论文列表JSSC 2024第12期Clocking & PLLs28nmVCO
A 75-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120 Multiply
提出一种低抖动和低参考杂散的75GHz次谐波注入锁定时钟倍频器
28nm CMOS, 7.5GHz, 67.7-fs rms jitter, -56.6 dBc reference spur, 2.33 mW
时钟倍频器注入锁定低抖动参考杂散CMOS
▸创新点1：采用复位和恢复操作优化参考注入（方法创新）。通过复位操作短路VCO输出以消除累积抖动，恢复操作修复波形失真，显著降低rms抖动至67.7 fs，同时减少参考杂散。
▸创新点2：使用校准环路最小化参考杂散（电路创新）。通过多环路校准精确控制VCO频率、恢复电平和时序，将参考杂散抑制至-56.6 dBc，提升系统纯净度。
▸创新点3：消除校准电路内部偏移（电路创新）。采用补偿技术抵消校准路径的固有偏移，确保频率控制和恢复时序的准确性，增强整体稳定性。
▸创新点4：实现超低功耗高性能指标（系统创新）。在28nm CMOS工艺下仅消耗2.33 mW，达成FoM -259.1 dB的业界领先水平，兼顾功耗与抖动/杂散性能。
Abstract
This article presents a subharmonic injection-locked
clock multiplier (SILCM) with low rms jitter and low refer-
ence spur. To improve rms jitter while suppressing reference
spur, reference injection is performed using two operations,
reset and recovery. During the reset operation, outputs of
voltage-controlled oscillator (VCO) are shorted to each other
to remove accumulated jitter. During the recovery operation,
the distorted VCO waveform caused by reset operation is
restored. To minimize refer