A −90-dBFS-IM3, −164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors

Abstract

This paper describes a continuous-time (CT) pipelined analog-to-digital converter (ADC) that represents a technology push along both—third-order distortion and noise—dimensions. Distortion is tackled using on-chip digital cancellation of static and timing digital-to-analog converter (DAC) mismatch errors. Low noise is achieved with design choices such as a resistive sub-DAC; a high-precision, on-chip, background-calibrated digital reconstruction filter (DRF); and a tunable LC lattice delay that allows a programmable sampling frequency. Implemented in a 16-nm FinFET process, the 6.4- GS/s prototype achieves an IM 3 of −90 dBFS and a small-signal NSD of −164 dBFS/Hz over a 700-MHz bandwidth, while dissipating 703-mW power. Such performance makes it suitable for high-performance instrumentation and communications that demand robustness to large interferers while digitizing small signals.