← 返回 JSSC 论文列表JSSC 2024第12期Data Converters16nmPipeline ADCDAC
A 90-dBFS-IM3 164-dBFSHz-NSD 700-MHz-Bandwidth Continuous-Time Pipelined ADC Wit
一款高性能连续时间流水线ADC，具有低失真和低噪声特性。
16nm FinFET, 6.4GS/s, -90dBFS IM3, -164dBFS/Hz NSD, 700MHz带宽, 703mW功耗
连续时间流水线ADC数字消除低噪声设计高精度校准可编程采样频率
▸采用片上数字消除技术处理静态和时序DAC失配误差
▸使用电阻子DAC和高精度数字重构滤波器降低噪声
▸可调LC晶格延迟实现可编程采样频率
Abstract
This paper describes a continuous-time (CT)
pipelined analog-to-digital converter (ADC) that represents
a technology push along both—third-order distortion and
noise—dimensions. Distortion is tackled using on-chip digital
cancellation of static and timing digital-to-analog converter
(DAC) mismatch errors. Low noise is achieved with design
choices such as a resistive sub-DAC; a high-precision, on-chip,
background-calibrated digital reconstruction filter (DRF); and a
tunable LC lattice delay that