JSSC 2024第12期RF & Wireless45-nm PD-SOI

Implementation and Application of Harmonic Reset Switching in Passive Mixers Sor

本文提出了一种在硬开关无源混频器中实现谐波抑制的合成方法。

34.8–64.5 mW, 0.25–4 GHz, 0.68 mm²

谐波抑制无源混频器硅绝缘体时钟频率谐波阻塞

▸创新点1：提出了一种针对硬开关无源混频器的谐波抑制（HR）合成方法，通过优化混频器结构，显著提高了谐波抑制能力，尤其是在高频段表现优异。

▸创新点2：创新性地集成了底部和顶部板混频技术，实现了天线节点和混频器输出端的双重谐波抑制，同时保持了低损耗和高效率。

▸创新点3：设计并实现了一种基于45nm部分耗尽型绝缘体上硅（PD-SOI）工艺的无源混频器接收机原型，在0.25-4GHz时钟频率下功耗仅为34.8-64.5mW，面积仅为0.68mm²，具有优异的谐波抑制性能。

▸创新点4：在1GHz时钟频率下，实现了第三和第五次谐波的1dB压缩点（B1dB）分别为+14dBm和+16.5dBm，谐波阻塞噪声系数（BNF）仅恶化3dB，显著提升了接收机的抗干扰能力。

Abstract

This article covers a synthesizing methodology for addressing harmonic rejection (HR) in hard-switching passive mixers. The integration of bottom and top plate mixing provides HR at both the antenna node and the output of the mixer in a passive and low-loss manner. A prototype mixer-first receiver (RX) in 45-nm partially depleted silicon-on-insulator (PD-SOI) is implemented, consuming 34.8–64.5 mW for clock frequencies ( fLO) of 0.25–4 GHz and occupying an active area of 0.68 mm 2. Due to the pa