A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

Abstract

A digital phase-locked loop (DPLL) using the feed- forward phase-error cancellation (FPC) is presented. The phase error of this DPLL using a digitally controlled ring oscillator is quickly canceled by a digitally controlled delay line (DCDL), which improves the phase noise performance. The loop gain of this FPC DPLL is also calibrated. In addition, a dead-zone-free (DZF) bang-bang phase-frequency detector (BBPFD) is presented to enhance the resolution of the time-to-digital converter (TDC). This proposed DPLL is fabricated in a 40-nm CMOS process which occupies 0.05 mm 2 . The measured rms jitter integrated from 1 kHz to 100 MHz is 788 fs at 1.6 GHz. The measured reference spur is −57.84 dBc for a 50 MHz reference frequency. Its power consumption is 5 mW for a 1.1-V supply voltage.