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A 16-GHz DPLL Using Feedforward Phase-Error Cancellation
提出一种采用前馈相位误差消除技术的16GHz数字锁相环，显著改善相位噪声性能。
40nm CMOS, 1.1V, 5mW, 788fs抖动(1kHz-100MHz), -57.84dBc参考杂散
数字锁相环前馈相位误差消除环形振荡器时间数字转换器Bang-Bang检测器
▸前馈相位误差消除技术(FPC)
▸无死区Bang-Bang相位频率检测器(DZF BBPFD)
▸环路增益校准
Abstract
A digital phase-locked loop (DPLL) using the feed-
forward phase-error cancellation (FPC) is presented. The phase
error of this DPLL using a digitally controlled ring oscillator
is quickly canceled by a digitally controlled delay line (DCDL),
which improves the phase noise performance. The loop gain of
this FPC DPLL is also calibrated. In addition, a dead-zone-free
(DZF) bang-bang phase-frequency detector (BBPFD) is presented
to enhance the resolution of the time-to-digital converter (TDC).
This