JSSC 2025第3期Data Converters65nmSAR ADCDelta-Sigma ADC

A 20-μs Turn-On Time 24-kHz Resolution 15100-MHz Digitally Programmable Temperat

一种基于快速锁定频率锁定环(FLL)和Δ-Σ分数分频器(FDIVs)的时钟发生器，具有20微秒启动时间和24kHz分辨率。

1.5–100 MHz可编程输出频率, 24kHz分辨率, 140ps峰峰值周期抖动, 6.8ppm/°C温漂

时钟发生器频率锁定环Δ-Σ分数分频器快速启动温度稳定性

▸使用SAR逻辑加速FLL锁定

▸采用截断误差消除(TEC)技术减少Δ-Σ引起的抖动

▸快速启动设计（20μs）

Abstract

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta- sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the ra