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A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge
提出一种新型SRAM-CIM结构，采用分段位线电荷共享方案，实现低能耗高信号容限的乘累加操作。
28nm CMOS, 7.2ns计算延迟, 22.75 TOPS/W能效
SRAM-CIM乘累加运算能效优化模拟数字转换器工艺变异
▸分段位线电荷共享(SBCS)方案
▸位线组合(BL-CMB)方案减少ADC数量
▸源注入局部乘法单元(SILMC)支持SBCS和BL-CMB
▸优先混合ADC抑制模拟读出面积和功耗
Abstract
Advances in static random access memory (SRAM)-
CIM devices are meant to increase capacity while improving
energy efficiency (EF) and reducing computing latency ( T
AC).
This work presents a novel SRAM-CIM structure using:
1) a segmented-bitline charge-sharing (SBCS) scheme for
multiply-and-accumulate (MAC) operations with low energy
consumption and a consistently high signal margin across MAC
values; 2) a bitline-combining (BL-CMB) scheme to reduce the
number of analog-to-digital converters (ADC