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A Jitter-Robust 40 Gbs ADC-Based Multicarrier Receiver Front-End With 4-GSs Base
一种抗抖动40Gbps多载波接收前端，采用4GS/s基带和优化ADC设计。
22nm FinFET, 40Gb/s, 1.6-ps rms抖动容限, BER<10-5, 3.05-pJ/bit能效
多载波接收机抗抖动ADC连续时间线性均衡器正交幅度调制
▸多载波信号处理技术实现时钟抖动要求的3倍放宽
▸采用可复位积分器减少信道间干扰
▸四路时间交织7位流水线-SAR ADC设计
Abstract
Demand for increased data rates in serial link
transceivers calls for innovative architectures capable of over-
coming impairments such as limited channel bandwidth (BW)
and stringent jitter specifications. This article presents a receiver
front-end (RXFE) architecture that supports multicarrier signal-
ing to provide a ∼3× relaxation in clock jitter requirements.
A total of 40 Gb/s data rate is supported by three 4-GS/s
bands with baseband (BB) four-level pulse amplitude modula-
tion (PAM4) and