A 5.94-µm Pixel-Pitch 25.2-Mpixel 120-Frames /s Full-Frame Global Shutter CMOS Image Sensor With Pixel-Parallel 14-bit ADC

Abstract

We present a 25.2-Mpixel, 120-frames /s full-frame global shutter CMOS image sensor (CIS) featuring pixel-parallel analog-to-digital converters (ADCs). The sensor addresses the limitations of conventional rolling shutters (RSs)—including motion distortion, flicker artifacts, and flash banding—while maintaining image quality suitable for professional and advanced amateur photography. A stacked architecture with 3- µm-pitch Cu–Cu hybrid bonding enables more than 50 million direct connections between the pixel array and the ADC circuits. The pixel-parallel single-slope ADCs operate with a comparator current of 25 nA and use a positive-feedback (PFB) scheme with noise-bandwidth control using an additional 11.4-fF capacitor, achieving 2.66 e− rms (166.8 µVrms) random noise (RN) at 0-dB gain with an REF slope of 2161 V /s. The 5.94- µm pixel pitch accommodates 30-bit latches designed under SRAM rules in a 40-nm CMOS process. Noise analysis reveals that in subthreshold operation, the dominant noise contributors are the comparator current, REF slope, and second-stage load capacitance. The sensor delivers 14-bit resolution, a 75.5-dB dynamic range (DR), and 120-frames /s operation at a power consumption of 1545 mW. A figure of merit of 0 .083 e− rms · pJ/step is comparable to state-of-the-art RS sensors. These results demonstrate that pixel- parallel ADC technology can be scaled to tens of megapixels while preserving high image quality and energy e fficiency, enabling motion-artifact-free