JSSC 2025第10期Other40nm

A 62–92-GHz 12.4% Efficiency Harmonics-Recycling CMOS Frequency Quadrupler Using Amplitude–Phase

本文提出了一种谐波回收CMOS四倍频器，实现高效率、宽带宽和大输出功率。

62-92 GHz带宽，12.4%峰值效率，11 dBm输出功率

谐波回收CMOS四倍频器高效率宽带宽

▸创新点1：谐波回收技术（HR）通过同时复用差模信号（f0, 3f0）和共模信号（4f0），显著提升效率至12.4%，属于电路创新。

▸创新点2：幅度-相位协调技术通过精确控制信号幅度和相位关系，抑制无用谐波（f0, 2f0, 3f0, 5f0），抑制深度达26.3-44.7 dBc，属于方法创新。

▸创新点3：模式交错峰值技术通过优化工作模式时序，扩展3 dB带宽至39%（62-92 GHz），属于系统级带宽优化创新。

▸创新点4：采用40nm CMOS工艺实现0.128 mm²核心面积，在毫米波频段（73 GHz）实现11 dBm输出功率，属于工艺与电路协同设计创新。

Abstract

This article presents a harmonics-recycling (HR) frequency quadrupler that achieves high efficiency, wide band- width, and large output power simultaneously. To improve the efficiency, both the differential-mode (f 0, 3f 0) and common-mode (4f 0) signals are reused by the harmonic recycler. Addition- ally, the amplitude–phase coordinating and mode-staggered-peak techniques are introduced to reject unwanted harmonics and expand the bandwidth. A proof-of-concept HR quadrupler is fabricated using 40-nm bulk CMOS. Measurement results show a 3-dB output power bandwidth of 39% (62–92 GHz), a peak efficiency of 12.4%, and a peak output power of 11 dBm at 73 GHz. The unwanted harmonics (f 0, 2f 0, 3f 0, and 5f 0) in measurement are rejected by more than 44.5, 44.7, 26.3, and 28 dBc, respectively. The core chip area is 0.128 mm 2, with a total area of 0.266 mm 2.