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A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Det
一款1024通道超低功耗尖峰排序芯片，采用事件驱动检测和空间聚类技术，适用于大规模神经记录。
0.00029-mm²/通道面积, 74-nW/通道功耗, 1000×数据压缩
尖峰排序超低功耗脑机接口空间聚类自组织映射
▸集成压缩ADC与两级尖峰检测器
▸利用高密度微电极阵列增强空间特征
▸改进的自组织映射算法实现低延迟实时操作
Abstract
This article presents a 1024-channel ultra-low-power
spike sorting chip featuring event-driven spike detection and
spatial clustering for large-scale neural recording. To address
power and scalability constraints in brain–computer interfaces
(BCIs), the design integrates a compressive analog-to-digital
converter (ADC) with a two-stage spike detector that significantly
reduces memory and processing activity. Spatial features derived
from high-density micro-electrode array (MEA) enhance cluster
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