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JSSC 2025第10期Analog Circuits65nmNeural Interface

A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels

一种采用TDMA和IIR-RLS自适应滤波器的神经记录SoC,实现834dB刺激伪迹抑制。
65nm CMOS, 4.9/4.8 µVrms噪声, 5.8 µW功耗
神经记录刺激伪迹消除TDMAIIR-RLS滤波器SoC
创新点1:16电极TDMA方案(系统创新) - 采用时分复用技术,通过单一共享模拟前端实现16个电极的神经信号记录,显著减少硬件复杂度和面积占用,每个记录电极AFE仅占0.0018 mm²,同时支持多通道并行处理。
创新点2:IIR-RLS自适应滤波器(算法创新) - 结合无限脉冲响应和递归最小二乘算法,实现高精度刺激伪迹消除,实时抑制100 mV刺激伪迹达83.4 dB,且校准收敛时间低于5.1秒,适用于256种通道传递函数组合。
创新点3:低功耗与高能效设计(电路创新) - 采用65 nm工艺,记录模式下功耗仅5.8 µW,SAC模块功耗为2.9 µW/TF,同时保持输入参考噪声低至4.9/4.8 µVrms(LFP/AP频段),SNDR影响仅0.8 dB。
创新点4:数字化辅助多电极系统(系统创新) - 集成数字化校准与实时处理功能,支持多通道刺激伪迹同步消除,兼顾高精度(83.4 dB抑制)与快速响应(<5.1 s收敛),适用于植入式神经接口应用。
Abstract
This article introduces a digitally-assisted, multi- electrode neural recording system equipped with a multi-channel stimulation artifact canceller (SAC) module. The system employs a 16-electrode time division multiple access (TDMA) scheme, allowing multiplexed neural signals to be recorded through a single shared analog front end (AFE). Simultaneously, it cancels stimulation artifacts from 16 stimulation electrodes using an infinite impulse response (IIR) recursive least squares (RLS) adaptive filter (AF). The proposed system-on-chip (SoC) is validated in vitro, demonstrating an instantaneous, real-time sup- pression of 100 mV stimulation artifacts by 83.4 dB, with rapid AF calibration convergence times under 5.1 s for 256 channel transfer function (TF) combinations. Fabricated using a 65 nm process, each recording electrode AFE occupies 0.0018 mm 2, achieves an input-referred noise of 4.9/4.8 µVrms for local field potential (LFP) and action potential (AP) bands respectively, and consumes 5.8 µW in recording mode. The SAC module consumes 2.9 µW/TF and minimally impacts recording signal- to-noise and distortion ratio (SNDR) by 0.8 dB. This results in a high-performing SAC chip, optimized for energy and area efficiency.