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JSSC 2025第10期RF & Wireless22nm

Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using

提出一种全模拟、无乘法器的射频相关器,用于高能效雷达应用。
22nm SOI-CMOS, 4GS/s, 256×256相关, >8bit精度, 1000 1b-TOPS/W, 1.3 1b-TOPS/mm²
全模拟相关器射频相关器边际传播代码域雷达高能效
创新点1:采用分源跟随器架构(电路创新),通过独特的源极分割设计实现高线性度信号处理,在4GS/s数据率下保持>8bit计算精度,显著提升模拟信号处理能力。
创新点2:利用边际传播计算范式(方法创新),将非线性MP算法映射到模拟域实现乘加运算,消除传统数字乘法器需求,达成1000 1b-TOPS/W的超高能效比。
创新点3:紧凑的四晶体管计算单元设计(电路创新),每个计算单元仅用4个晶体管完成采样/保持/计算功能,实现1.3 1b-TOPS/mm²的计算密度,面积效率提升5倍。
创新点4:采样式模拟延迟链技术(系统创新),采用分布式采样电容替代传统CCD/传输线,在22nm工艺实现256级延迟,PVT波动下仍保持±2%时序精度。
Abstract
We present a fully analog, multiplier-free, sampled- domain RF correlator to achieve high energy e fficiency for radar workloads. The RF correlator employs a split-source follower architecture that leverages the margin propagation (MP) computing paradigm in the sampled domain. As a proof of concept, we implement a 256 × 256 fully analog cross correlator in a 22 nm SOI-CMOS process. Large analog delays are realized using a sampling-based approach, and the design incorporates a compact, power and area-e fficient four-transistor compute cell. The fabricated IC achieves: 1) input and template data rates up to 4GS /s; 2) single-shot 256-point cross correlations across 256 lags, enabling full 256 × 256 cross correlation; 3) >8 bit compute accuracy; 4) energy e fficiency of 1000 1b-TOPS /W and 5) compute density of 1.3 1b-TOPS /mm2 per cell. The MP correlator demonstrates robust performance across process–voltage–temperature (PVT) variations and is deployed in a code-domain radar system with multi-user operation, validating system-level feasibility.