JSSC 2025第11期Data Converters65nm

A 2 Time-Interleaved 4-GSs 14-Bit DAC With On-Chip Calibration of Interleaving N

一种带片上校准的2×时间交织14位4GS/s DAC，通过两步校准提升SFDR至61dB。

14-bit 4-GS/s, SFDR ≥ 61dB@第一奈奎斯特区

时间交织DAC电流导向型片上校准无杂散动态范围占空比误差

▸提出基于时域建模的SFDR综合函数，准确分析交织误差对高分辨率TI-DAC的影响

▸采用低复杂度电路的两步前台校准方案，解决窄带锁定导致的SFDR退化问题

▸提出紧凑型循环量化电路结合均匀网格搜索算法，实现高精度占空比误差校准

Abstract

This work presents a high-linearity 2× time- interleaved (TI) current-steering (CS) digital-to-analog converter (DAC) facilitated by an on-chip calibration approach. In order to accurately analyze the impact of interleaving errors on high- resolution TI-DAC, a comprehensive function of spurious-free dynamic range (SFDR) is derived from time-domain modeling. Based on theoretical analysis, a foreground two-step calibration scheme with low-complexity circuits is proposed to address the issue of SFD