JSSC 2025第11期Other40nm

A 62–92-GHz 12.4% Efficiency Harmonics-Recycling CMOS Frequency Quadrupler Using Amplitude–Phase

本文提出了一种谐波回收频率四倍器，实现了高效率、宽带宽和大输出功率。

40-nm CMOS, 12.4% peak efficiency, 11 dBm peak output power at 73 GHz

谐波回收频率四倍器CMOS高效率宽带宽

▸创新点1：谐波回收技术（电路创新） - 通过同时复用差模信号（f0, 3f0）和共模信号（4f0），显著提升效率至12.4%，并实现11 dBm峰值输出功率，解决了传统倍频器能量浪费问题。

▸创新点2：幅相协调技术（方法创新） - 通过精确控制信号幅度与相位关系，抑制无用谐波（如f0, 2f0, 3f0, 5f0），实测谐波抑制达26.3-44.7 dBc，提升频谱纯度。

▸创新点3：模式交错峰值技术（系统创新） - 采用多模式工作点动态匹配，扩展3-dB带宽至39%（62-92 GHz），突破传统倍频器带宽受限的瓶颈。

▸创新点4：紧凑型CMOS集成（工艺创新） - 基于40-nm CMOS工艺实现0.128 mm²核心面积，在毫米波频段达成高集成度与低成本平衡。

Abstract

This article presents a harmonics-recycling (HR) frequency quadrupler that achieves high efficiency, wide band- width, and large output power simultaneously. To improve the efficiency, both the differential-mode (f 0, 3f 0) and common-mode (4f 0) signals are reused by the harmonic recycler. Addition- ally, the amplitude–phase coordinating and mode-staggered-peak techniques are introduced to reject unwanted harmonics and expand the bandwidth. A proof-of-concept HR quadrupler is fabricated using 40-nm bulk CMOS. Measurement results show a 3-dB output power bandwidth of 39% (62–92 GHz), a peak efficiency of 12.4%, and a peak output power of 11 dBm at 73 GHz. The unwanted harmonics (f 0, 2f 0, 3f 0, and 5f 0) in measurement are rejected by more than 44.5, 44.7, 26.3, and 28 dBc, respectively. The core chip area is 0.128 mm 2, with a total area of 0.266 mm 2.