JSSC 2025第11期Other40nm

A 62–92-GHz 12.4% Efficiency Harmonics-Recycling CMOS Frequency Quadrupler Using Amplitude–Phase

本文提出了一种谐波回收频率四倍器，实现了高效率、宽带宽和大输出功率。

40-nm CMOS, 12.4% peak efficiency, 11 dBm peak output power at 73 GHz

谐波回收频率四倍器CMOS高效率宽带宽

▸谐波回收技术

▸幅相协调技术

▸模式交错峰值技术

Abstract

This article presents a harmonics-recycling (HR) frequency quadrupler that achieves high efficiency, wide band- width, and large output power simultaneously. To improve the efficiency, both the differential-mode (f 0, 3f 0) and common-mode (4f 0) signals are reused by the harmonic recycler. Addition- ally, the amplitude–phase coordinating and mode-staggered-peak techniques are introduced to reject unwanted harmonics and expand the bandwidth. A proof-of-concept HR quadrupler is fabricated using 4