← 返回 JSSC 论文列表JSSC 2025第11期Clocking & PLLs22nm FD-SOI
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW
一款采用22nm FD-SOI工艺的49-63 GHz双PLL锁相步进调频连续波雷达收发器
EIRP 9dBm, PN -101.09dBc/Hz@1MHz, RX NF 10dB, 测距5m, 分辨率1.4cm
毫米波雷达FMCW双PLL硅基绝缘体相控阵
▸双PLL架构实现宽带宽
▸支持自由运行和锁相操作
▸集成线性阵列串馈贴片天线
Abstract
A 49–63 GHz phase-locked stepped chirp frequency
modulated continuous wave (FMCW) radar transceiver (TRX)
in a 22-nm fully depleted silicon on insulator (FD-SOI) process
is presented. To achieve the desired large bandwidth (BW), the
frequency range is split into two sub-chirps, each controlled
by distinct phase-locked loops (PLLs)—a reference PLL and a
mixing PLL. This novel dual-PLL architecture facilitates a wide
effective BW without the need for designing ultra-wideband
TRX blocks. This radar