A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW

Abstract

A 49–63 GHz phase-locked stepped chirp frequency modulated continuous wave (FMCW) radar transceiver (TRX) in a 22-nm fully depleted silicon on insulator (FD-SOI) process is presented. To achieve the desired large bandwidth (BW), the frequency range is split into two sub-chirps, each controlled by distinct phase-locked loops (PLLs)—a reference PLL and a mixing PLL. This novel dual-PLL architecture facilitates a wide effective BW without the need for designing ultra-wideband TRX blocks. This radar TRX supports both free-running and phase-locked operations. The CMOS chip is co-integrated with linear arrays of series-fed patch antennas for each frequency band. The measured effective isotropic radiated power (EIRP) is 9 dBm with a phase noise (PN) of −101.09 dBc/Hz at 1 MHz offset at 56 GHz. The receiver (RX) achieves a 10-dB noise figure (NF). The radar field measurement demonstrates a maximum distance of 5 m and a range resolution of 1.4 cm.