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JSSC 2025第11期Clocking & PLLs28nm

A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique Yumeng Yang

提出一种具有自适应频率滤波的低杂散低抖动分数输出分频器,用于DTC增益和INL背景校准。
28nm CMOS, 0.084 mm², 10-300 MHz, -80 dBc
分数输出分频器自适应频率滤波DTC增益校准INL背景校准低杂散低抖动
自适应频率滤波技术
DTC增益和INL背景校准
辅助PLL的离散时间模型
Abstract
An open-loop fractional output divider (FOD) with self-adaption frequency filtering for digital-to-time converter (DTC) gain and integrated non-linearity (INL) background calibration is presented in this article. The DTC is usually adopted in the FOD to compensate the quantization error. However, the delay of the DTC is sensitive to process, voltage, and temperature (PVT) variations, which necessities gain and INL calibrations. The existing FODs can only perform gain calibration or require prior